1. Field of the Invention
The present invention relates to a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor), and more particularly, to a trench power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and method for fabricating the power MOSFET.
2. Description of Related Art
A power MOSFET can be applied to be a high voltage device with the operation voltage up to over 4,500 volts. The methods for fabricating the conventional power device are similar to the general methods used for semiconductor fabrication, and its gate is formed on the surface of the silicon substrate, i.e. a planar gate. However, for the planar gate, the design of minimal gate length may hinder the increase of the device intensity. Therefore, the trench gate structure, which may greatly reduce the device size, has become the trend in power device fabrication.
FIGS. 1A–1I are the cross sectional views for the fabrication processes of the conventional trench power MOSFET (Metal Oxide Semiconductor Field Effect Transistor).
First, referring to FIG. 1A, a silicon oxide layer 104 is formed on the substrate 100 which contains an epitaxial layer 102.
Then, referring to FIG. 1B, the epitaxial layer 102 and the silicon oxide layer 104 are patterned, in order to form a trench 106.
The following step, referring to FIG. 1C, an etching process is undertaken to remove the silicon oxide layer 104. Thereafter, a gate oxide layer 108 is formed to cover the surfaces of the epitaxial layer 102 and the trench 106. Then, a polysilicon 110 is formed to fill in the trench 106.
Referring to FIG. 1D, an etching back process is undertaken to remove a part of the polysilicon layer 110 until the gate oxide layer 108 is exposed. The filled polysilicon 110a inside the trench 106 functions as the gate electrode for the trench power MOSFET. Later on, an ion implantation process is performed to form the body well region 112 between both sides of the trench 106 and inside the epitaxial layer 102 (as shown in FIG. 1E).
Then, referring to FIG. 1F, after forming a photoresist layer (not shown) on the substrate 100 and defining the photoresist layer, a patterned photoresist layer 114 is formed.
Please further referring to 1G, the patterned photoresist layer 114 is used as a mask for ion implantation to form the source region 116. Later on, the patterned photoresist layer 114 is removed and a dielectric layer 118 is formed over the substrate 100.
Referring to FIG. 1H, a photolithography etching process is carried out to remove a part of the dielectric layer 118 to form a contact opening 120 inside the dielectric layer 118. In addition, the contact opening 120 exposes a portion of the surface of the body well region 112 that is preserved for the body region.
Finally, referring to FIG. 1I, the dielectric layer 118a is used as a mask for ion implantation to form the body region 122 inside the body well region 112.
In previous mentioned fabrication process for the trench power MOSFET, in order to form the source region 116, it is necessary to form the patterned photoresist layer 114 on the substrate 100 (as shown in FIG. 1F) and the patterned photoresist layer 114 is used as a mask for ion implantation to form the source region 116 inside the body well region 112. However, following demands for higher integration, the critical dimension (CD) of the device becomes smaller. The previously mentioned patterned photoresist layer 114 may collapse or peel due to its small size, which further leads to deviation of the defined pattern. Besides, during the formation of the source region 116, the patterned photoresist layer 114 can easily be damaged by high current implantor during the ion implementation process, which can cause errors for definition.
In addition, if over-etching happens to the polysilicon layer 110 during the etching back process for removing a part of the polysilicon layer 110 (as shown in FIG. 1D), dopants may be implanted from the sidewalls of the trench during the following ion implantation process for the formation of the source region 116, thus leading to current leakage.
Besides, if misalignment occurs during the process for defining the photoresist layer, the subsequently formed source region 116 will be asymmetric.
Furthermore, during the formation of the contact window opening 120 (as shown in the FIG. 1H), misalignment is likely to happen, which causes abnormal electrical connection and reduce the reliability of devices.